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this is information on a product in full production. may 2013 docid17892 rev 2 1/24 24 L6391 high voltage high and low-side driver datasheet - production data features ? high voltage rail up to 600 v ? dv/dt immunity 50 v/nsec in full temperature range ? driver current capability: ? 290 ma source ? 430 ma sink ? switching times 75/35 nsec rise/fall with 1 nf load ? 3.3 v, 5 v ttl/cmos inputs with hysteresis ? integrated bootstrap diode ? comparator for fault protections ? smart shutdown function ? adjustable deadtime ? interlocking function ? compact and simplified layout ? bill of material reduction ? effective fault protection ? flexible, easy and fast design applications ? motor driver for home appliances, factory automation, industrial drives and fans ? hid ballasts, power supply units description the L6391 is a high voltage device manufactured with the bcd? ?off-line? technology. it is a single-chip half-bridge gate driver for n-channel power mosfet or igbt. the high-side (floating) section is designed to stand a voltage rail up to 600 v. the logic inputs are cmos/ttl compatible down to 3.3 v for easy interfacing microcontroller/dsp. an integrated comparator is available for protections against overcurrent, overtemperature, etc. table 1. device summary order code package packaging L6391n (1) dip-14 tube L6391d so-14 tube L6391dtr so-14 tape and reel 1. package option for evaluation only, not available for production. www.st.com
contents L6391 2/24 docid17892 rev 2 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 9 bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 c boot selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid17892 rev 2 3/24 L6391 block diagram 1 block diagram figure 1. block diagram 89 '(7(&7,21 /(9(/ 6+,)7(5 %227675$3'5,9(5 6 9 && /9* '5,9(5 +,1 /,1 +9* '5,9(5 +9* 287 /9 * %227 89 '(7(&7,21 *1' 6'2' '7 '($' 7,0( 5 /2*,& 6+227 7+528*+ 35(9(17,21 )/2$7,1*6758&785( &203$5$725 &3 iurp/9* 9&& 9 9 &3 60$57 6' $0y
pin connection L6391 4/24 docid17892 rev 2 2 pin connection figure 2. pin connection (top view) table 2. pin description pin number pin name type function 1 lin i low-side driver logic input (active low) 2 sd /od (1) i/o shutdown logic input (active low)/open-drain comparator output 3 hin i high-side driver logic input (active high) 4 vcc p lower section supply voltage 5 dt i deadtime setting 6 nc not connected 7 gnd p ground 8 cp- i comparator negative input 9 cp+ i comparator positive input 10 lvg (1) 1. the circuit guarantees less than 1 v on the lvg and hvg pins (@ i sink = 10 ma), with v cc > 3 v. this allows omitting the ?bleeder? resistor connected betw een the gate and the source of the external mosfet normally used to hold the pin low; the gate driver assures low impedance also in sd condition. o low-side driver output 11 nc not connected 12 out p high-side (floating) common voltage 13 hvg (1) o high-side driver output 14 boot p bootstrapped supply voltage lin hin lvg hvg dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking g in edge deadtime interlocking interlocking g i g gate driver outputs off (half-bridge tri-state) 9&& +,1 /,1 6'2' 1& 287 +9* %227 *1' '7 &3 /9* &3 1& $0y
docid17892 rev 2 5/24 L6391 truth table 3 truth table note: x: don't care table 3. truth table input output sd lin hin lvg hvg lxxll hhl l l hlhll hllhl hhhlh
electrical data L6391 6/24 docid17892 rev 2 4 electrical data 4.1 absolute maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol parameter value unit min. max. v cc supply voltage -0.3 21 v v out output voltage v boot - 21 v boot + 0.3 v v boot bootstrap voltage -0.3 620 v v hvg high-side gate output voltage v out - 0.3 v boot + 0.3 v v lvg low-side gate output voltage -0.3 v cc + 0.3 v v cp- comparator negative input voltage -0.3 v cc + 0.3 v v cp+ comparator positive input voltage -0.3 v cc + 0.3 v v i logic input voltage -0.3 15 v v od open-drain voltage -0.3 15 v dv out / dt allowed output slew rate 50 v/ns p tot total power dissipation (ta = 25 c) 800 mw t j junction temperature 150 c t stg storage temperature -50 150 c esd hbm (human body model) 2 kv table 5. thermal data symbol parameter so-14 dip-14 unit r th(ja) thermal resistance junction-to-ambient 165 100 c/w
docid17892 rev 2 7/24 L6391 electrical data 4.3 recommended operating conditions table 6. recommended operating conditions symbol pin parameter test conditions min. max. unit v cc 4 supply voltage 12.5 20 v v bo (1) 1. v bo = v boot - v out . 14-12 floating supply voltage 12.4 20 v v out 12 dc output voltage - 9 (2) 2. lvg off. v cc = 12.5 v. logic is operational if v boot > 5 v. 580 v v cp- 8 comparator negative input voltage v cp+ [ 2.5 v] v cc (3) 3. at least one of the comparator's inputs must be lower than 2.5 v to guarantee proper operation. v v cp+ 9 comparator positive input voltage v cp- [ 2.5 v] v cc (3) v f sw switching frequency hvg, lvg load c l = 1 nf 800 khz t j junction temperature -40 125 c
electrical characteristics L6391 8/24 docid17892 rev 2 5 electrical characteristics 5.1 ac operation table 7. ac operation electrical characteristics (v cc = 15 v; t j = +25 c) symbol pin parameter test conditions min. typ. max. unit t on 1 vs 10 3 vs 13 high/low-side driver turn-on propagation delay v out = 0 v v boot = vcc c l = 1 nf v i = 0 to 3.3 v see figure 3 50 125 200 ns t off high/low-side driver turn-off propagation delay 50 125 200 ns t sd 2 vs 10, 13 shutdown to high/low-side driver propagation delay 50 125 200 ns t isd comparator triggering to high/low-side driver turn-off propagation delay measured applying a voltage step from 0 v to 3.3 v to pin cp+; cp- = 0.5 v 200 250 ns mt delay matching, hs and ls turn-on/off 30 ns dt 5 deadtime setting range see figure 4 r dt = 0 , c l = 1 nf 0.1 0.18 0.25 s r dt = 37 k , c l = 1 nf, c dt = 100 nf 0.48 0.6 0.72 s r dt = 136 k , c l = 1 nf, c dt = 100 nf 1.35 1.6 1.85 s r dt = 260 k , c l = 1 nf, c dt = 100 nf 2.6 3.0 3.4 s mdt matching deadtime (1) r dt = 0 , c l = 1 nf 80 ns r dt = 37 k , c l = 1 nf, c dt = 100 nf 120 ns r dt = 136 k , c l = 1 nf, c dt = 100 nf 250 ns r dt = 260 k , c l = 1 nf, c dt = 100 nf 400 ns t r 10,13 rise time c l = 1 nf 75 120 ns t f fall time c l = 1 nf 35 70 ns 1. mdt = | dt lh - dt hl | (see figure 5 ).
docid17892 rev 2 9/24 L6391 electrical characteristics figure 3. timing figure 4. typical deadtime vs. dt resistor value hin hvg 50% 10% 90% 50% t r t f t on t off 90% 10% lin lvg 50% 10% 90% 50% t r t f t on t off 90% 10% lvg/hvg sd 90% 50% t f t sd 10% 0 0.5 1 1.5 2 2.5 3 3.5 0 50 100 150 200 250 300 rdt (kohm) dt (us) approximated formula for rdt calculation (typ.): rdt[k ] = 92.2 dt[s] - 16.6 am16763v1
electrical characteristics L6391 10/24 docid17892 rev 2 5.2 dc operation table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) symbol pin parameter test conditions min. typ. max. unit v cc_hys 4 v cc uv hysteresis 1.2 1.5 1.8 v v cc_thon v cc uv turn-on threshold 11.5 12 12.5 v v cc_thoff v cc uv turn-off threshold 10 10.5 11 v i qccu undervoltage quiescent supply current v cc = 9.5 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+ = gnd; cp- = 5 v 100 150 a i qcc quiescent current v cc = 15 v sd = 5 v; lin = 5 v; hin = gnd; r dt = 0 ; cp+ = gnd; cp- = 5 v 500 1000 a bootstrapped supply voltage section (1) v bo_hys 14-12 v bo uv hysteresis 1.2 1.5 1.8 v v bo_thon v bo uv turn-on threshold 10.6 11.5 12.4 v v bo_thoff v bo uv turn-off threshold 9.1 10 10.9 v i qbou undervoltage v bo quiescent current v bo = 9 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+ = gnd; cp- = 5 v 70 110 a i qbo v bo quiescent current v bo = 15 v sd = 5 v; lin and hin = 5 v; r dt = 0 ; cp+ = gnd; cp- = 5 v 200 240 a i lk high voltage leakage current v hvg = v out = v boot = 600 v 10 a r ds(on) bootstrap driver on resistance (2) lvg on 120 w driving buffer section i so 10, 13 high/low-side source short- circuit current v in = v ih (t p < 10 s) 200 290 ma i si high/low-side sink short- circuit current v in = v il (t p < 10 s) 250 430 ma
docid17892 rev 2 11/24 L6391 electrical characteristics logic inputs v il 1, 2, 3 low level logic threshold 0.8 1.1 v v ih high level logic threshold voltage 1.9 2.25 v v il_s 1, 3 single input voltage lin and hin connected together and floating 0.8 v i hinh 3 hin logic ?1? input bias current hin = 15 v 110 175 260 a i hinl hin logic ?0? input bias current hin = 0 v 1 a i linl 1 lin logic ?0? input bias current lin = 0 v 3 6 20 a i linh lin logic ?1? input bias current lin = 15 v 1 a i sdh 2 sd logic ?1? input bias current sd = 15 v 10 40 100 a i sdl sd logic ?0? input bias current sd = 0 v 1 a 1. v bo = v boot - v out . 2. r ds(on) is tested in the following way: r ds(on) = [(v cc - v cboot1 ) - (v cc - v cboot2 )] / [i 1 (v cc ,v cboot1 ) - i 2 (v cc ,v cboot2 )] where i 1 is pin 14 current when v cboot = v cboot1 , i 2 when v cboot = v cboot2 . table 9. sense comparator (1) (v cc = 15 v, t j = +25 c) symbol pin parameter test conditions min. typ. max. unit v io 8, 9 input offset voltage -15 15 mv i ib 8, 9 input bias current v cp+ = 1 v, v cp - = 0.5 v 1 a v ol 2 open-drain low level output voltage i od = - 3 ma v cp + = 1 v; v cp - = 0.5 v; 0.5 v t d_comp comparator delay r pull = 100 k to 5 v on sd /od pin; v cp - = 0.5 v; voltage step on cp+ = 0 to 3.3 v 90 130 ns sr 2 slew rate c l = 180 pf; r pu = 5 k 60 v/ s 1. comparator is disabled when v cc is in uvlo condition. table 8. dc operation electrical characteristics (v cc = 15 v; t j = + 25 c) (continued) symbol pin parameter test conditions min. typ. max. unit
waveform definitions L6391 12/24 docid17892 rev 2 6 waveform definitions figure 5. deadtime and interlocking waveform definitions lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg lin hin lvg hvg dt lh dt hl dt lh dt hl dt lh dt hl dt lh dt hl gate driver outputs off (half-bridge tri-state) interlocking interlocking g in control signal edge overlapped: interlocking + deadtime control signal edge synchronous (*): deadtime control signal edge not overlapped, but inside the deadtime: deadtime control signal edge not overlapped, outside the deadtime: direct driving (*) hin and lin can be connected togheter and driven by just one control signal interlocking interlocking g i g gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state) gate driver outputs off (half-bridge tri-state)
docid17892 rev 2 13/24 L6391 smart shutdown function 7 smart shutdown function the L6391 integrates a comparator committed to the fault sensing function. both comparator's inputs are available on pins 8 and 9. for example, applying a voltage reference to cp- and connecting the cp+ to an external shunt resistor, a simple overcurrent detection function can be implemented. the output signal of the comparator is fed to an integrated mosfet with the open-drain output available on pin 2, shared with the sd input. when the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the half- bridge in tri-state. figure 6. smart shutdown timing waveforms sd/od from/to controller v bias c sd r sd smart sd logic r on_od shutdown circuit r pd_sd an approximation of the disable time is given by: where: hin/lin hvg/lvg open-drain gate (internal) cp+ cp- protection fast shutdown : the driver outputs are set in sd state immediately after the comparator triggering even if the sd signal has not yet reached the lower input threshold disable time sd/od am16755v1
smart shutdown function L6391 14/24 docid17892 rev 2 in common overcurrent protection architectures, the comparator output is usually connected to the sd input and an rc network is connected to this sd /od line in order to provide a monostable circuit, which implements a protection time following the fault condition. differently from the common fault detection systems, the L6391 smart shutdown architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing the propagation delay between the fault detection event and the current output switch-off. in fact the time delay between the fault and the output turn-off is no longer dependent on the rc value of the external network connected to the sd /od pin. in the smart shutdown circuitry, the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. at the same time, the internal logic turns on the open-drain output and holds it on until the sd voltage goes below the sd logic input lower threshold. when such threshold is reached, the open-drain output is turned off, allowing the external pull-up to recharge the capacitor. the driver outputs restart following the input pins as soon as the voltage at the sd /od pin reaches the higher threshold of the sd logic input. the smart shutdown system gives the possibility to increase the time constant of the external rc network (that determines the disable time after the fault event) up to very large values without increasing the delay time of the protection. any external signal provided to the sd pin is not latched and can be used as control signal in order to perform, for instance, pwm chopping through this pin. in fact when a pwm signal is applied to the sd input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. in some applications, it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. this may, for example, be achieved by a circuit as the one shown in figure 7 . when the open-drain starts pulling down the sd /od pin, the external latch turns on and keeps the pin to gnd, preventing it from being pulled up again once the sd logic input lower threshold is reached and the internal open-drain turns off. one pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the sd /od pin. figure 7. protection latching circuit in applications using only one L6391 for the protection of different legs (such as a single- shunt inverter, for example), the resistor divider, shown in figure 8 , can be implemented. this simple network allows the sd pins of the other devices to reach a voltage lower than L6391 v il , so that each device can get its low logic level regardless of part-to-part variations of the thresholds. sd_sense sd_force gnd vdd c vdd vcc r1 9*r r3 2*r hvg out lvg vboot cp- opout dt cp+ L6391 sd/od gnd vcc hin lin + + - vcc hv bus l639x l639x sd/od sd/od c2 c3 c1 c2, c3: small noise filtering capacitors c1: disable time setting capacitor r2 r v bias am16756v1
docid17892 rev 2 15/24 L6391 smart shutdown function figure 8. sd level shifting circuit sd_reset sd_force/sense gnd vdd c 3.3 / 5 v 3.3 / 5 v r1 20 k r2 1.5 k r3 2.2 k r4 20 k hvg out lvg vboot cp- opout dt cp+ L6391 sd/od gnd vcc hin lin + + - vcc to other driver/devices am16757v1
typical application diagram L6391 16/24 docid17892 rev 2 8 typical application diagram figure 9. application diagram uv detection level sh i fter bootstrap driver s v cc lvg driv er hin lin hvg driver hvg out lvg boot uv detection gnd sd/od dt dead time r logic shoot thr o ugh preve ntion floati ng structure co m pa rator cp+ 1 2 10 14 7 5 3 4 9 from lvg vcc 5v + - 5v cp - 8 12 13 h.v. to load cboot v bias v cc + from controller from controller fr om / to controller v bias sm a rt sd am02458v1
docid17892 rev 2 17/24 L6391 bootstrap driver 9 bootstrap driver a bootstrap circuitry is needed to supply the high voltage section. this function is usually accomplished by a high voltage fast recovery diode ( figure 10 ). in the L6391 a patented integrated structure replaces the external diode. it is realized by a high voltage dmos, driven synchronously with the low-side driver (lvg), with diode in series, as shown in figure 11 . an internal charge pump ( figure 11 ) provides the dmos driving voltage. 9.1 c boot selection and charging to choose the proper c boot value the external mos can be seen as an equivalent capacitor. this capacitor c ext is related to the mos total gate charge: equation 1 the ratio between the capacitors c ext and c boot is proportional to the cyclical voltage loss. it has to be: equation 2 if q gate is 30 nc and v gate is 10 v, c ext is 3 nf. with c boot = 100 nf the drop is 300 mv. if hvg has to be supplied for a long time, the c boot selection has also to take into account the leakage and quiescent losses. hvg steady-state consumption is lower than 240 a, so if hvg t on is 5 ms, c boot has to supply c ext with 1.2 c. this charge on a 1 f capacitor means a voltage drop of 1.2 v. the internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). this structure can work only if v out is close to gnd (or lower) and in the meanwhile the lvg is on. the charging time (t charge ) of the c boot is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. the bootstrap driver introduces a voltage drop due to the dmos r ds(on) (typical value: 120 ). at low frequency this drop can be neglected. anyway, the rise of frequency has to take into account. the following equation is useful to compute the drop on the bootstrap dmos: equation 3 where q gate is the gate charge of the external power mos, r ds(on) is the on resistance of the bootstrap dmos and t charge is the charging time of the bootstrap capacitor. c ext q gate v gate ------------- - = c boot >>>c ext v drop i ch e arg r ds on () v drop q gate t ch e arg ------------------ r ds on () ==
bootstrap driver L6391 18/24 docid17892 rev 2 for example: using a power mos with a total gate charge of 30 nc the drop on the bootstrap dmos is about 1 v, if the t charge is 5 s. in fact: equation 4 v drop has to be taken into account when the voltage drop on c boot is calculated: if this drop is too high, or the circuit topology doesn?t allow a sufficient charging time, an external diode can be used. figure 10. bootstrap driver with high voltage fast recovery diode figure 11. bootstrap driver with internal charge pump v drop 30nc 5 s -------------- - 120 0.7v ? = to load h.v. hvg lvg c boot d boot boot v cc out hvg lvg to load h.v. c boot v cc out boot
docid17892 rev 2 19/24 L6391 package mechanical data 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their level of environmental compliance. ecopack? specifications, grade definitions and product status are available at: www.st.com. ecopack? is an st trademark. note: ?d? and ?e1? dimensions do not include mold flash or protusions. mold flash or protusions don?t have to exceed 0.25 mm. table 10. dip-14 mechanical data dim. mm min. typ. max. a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 18.67 19.05 19.69 e 7.62 7.87 8.26 e1 6.10 6.35 7.11 e 2.54 e1 15.24 ea 7.62 eb 10.92 l 2.92 3.30 3.81
package mechanical data L6391 20/24 docid17892 rev 2 figure 12. dip-14 package dimensions 0015893_e
docid17892 rev 2 21/24 L6391 package mechanical data table 11. so-14 mechanical data dim. mm min. typ. max. a 1.35 1.75 a1 0.10 0.25 a2 1.10 1.65 b 0.33 0.51 c 0.19 0.25 d 8.55 8.75 e 3.80 4.00 e 1.27 h5.80 6.20 h0.25 0.50 l 0.40 1.27 k 0 8 e0.40 ddd 0.10
package mechanical data L6391 22/24 docid17892 rev 2 figure 13. so-14 package dimensions 0016019_e
docid17892 rev 2 23/24 L6391 revision history 11 revision history table 12. document revision history date revision changes 14-dec-2010 1 first release. 10-may-2013 2 added hbm parameter to table 4 . added i qbo max. value to table 8 . changed v il and v ih min. and max. values in table 8 . added note to table 9 . updated section 7 and section 9.1 . changed figure 6 and added figure 7 and figure 8 . updated so-14 mechanical data. updated dip-14 mechanical data.
L6391 24/24 docid17892 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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